1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a semiconductor device realizing high speed operation with a low voltage.
2. Description of the Background Art
During these few past years, reduction in the level of a power supply voltage is required to reduce element breakdown voltage due to reduction in consumption power and miniaturization of elements. However, the operating speed of an MOS transistor is reduced since the threshold voltage cannot be neglected at a low voltage. The threshold voltage is reduced in an active state to prevent this delay. Reduction in the threshold voltage poses the problem of increase in leakage current due to subthreshold current of an MOS transistor in a standby state. In view of this problem, Japanese Patent Laying-Open No. 5-108194 discloses a low consumption power type integrated semiconductor device directed to provide an information processor that can operate at high speed even with a low power supply voltage in an active state and that has consumption power due to leakage current reduced in a standby state.
FIG. 15 shows an embodiment of this low consumption power type integrated semiconductor device described in Japanese Patent Laying-Open No. 5-108194.
Referring to FIG. 15, the threshold value of an MOS transistor (MN, MP) is set to a low value in order to maintain high speed operation at a low power supply voltage. The device enters a standby mode by a program command or an external control signal upon determination of no keyboard input for more than a predetermined time period or continuation of a low consumption power state for more than a predetermined time period.
In a standby mode, a clock control circuit 3 suppresses application of a clock Ckm to an MPU (Microprocessor Unit) 1. At the same time, the provision of an operation mode switching signal A activates basic bias circuits 2-1 and 2-2, whereby a negative substrate bias VBn and a substrate bias VBp more positive than the power supply voltage are applied to an NMOS transistor (MN) and a P channel MOS transistor (MP), respectively. The application of a substrate bias causes the threshold value of the MOS transistor to be increased, whereby the leakage current is lowered in an exponential function by the increased threshold value. That is to say, application of a substrate bias improves the subthreshold characteristic to reduce leakage current. Reduction in leakage current is greater in proportion to a greater number of elements in the microprocessor. The value becomes greater than the consumption power of substrate bias circuits 2-1 and 2-2. Thus, an information processor that can operate at high speed with low voltage and that has low consumption power during a standby mode is available.
However, the conventional low consumption power type integrated semiconductor device shown in FIG. 15 has problems set forth in the following. Since a positive substrate bias VBp and a negative substrate bias VBn are applied to a PMOS transistor (MP) and an NMOS transistor (MN), respectively, in a standby state, reverse bias is established between the source and substrate to increase the depletion layer. Although the threshold voltage is boosted in a standby state, a short channel effect becomes noticeable as the scale of integration is increased for the low consumption power type integrated semiconductor device. This poses the problem that leakage current based on the subthreshold current of the MOS transistor in a standby state, and in turn consumption power, will not be reduced sufficiently.
An object of the present invention is to provide a semiconductor device that has high threshold voltage and that can have consumption power due to leakage current by short channel effect reduced in a standby state, and that has the threshold voltage reduced and that can operate at high speed with low power supply voltage in an active state.
According to an aspect of the present invention, a semiconductor device includes a P channel MOS transistor having a standby state and an active state, an N channel MOS transistor having a standby state and an active state, a first potential supply circuit providing a 0 or positive potential to a substrate of the P channel MOS transistor on the basis of a potential of a source electrode thereof when the P channel MOS transistor attains a standby state, a second potential supply circuit for supplying a negative potential having an absolute value lower than a built-in potential to the substrate of P channel MOS transistor on the basis of a potential of the source electrode of the P channel MOS transistor, a third potential supply circuit for supplying a 0 or negative potential to a substrate of the N channel MOS transistor on the basis of a potential of a source electrode thereof when the N channel MOS transistor attains a standby state, and a fourth potential supply circuit for supplying a positive potential having an absolute value lower than a built-in potential to the substrate of the N channel MOS transistor on the basis of a potential of the source electrode of the N channel MOS transistor.
According to the above-described semiconductor device, the P channel MOS transistor and the N channel MOS transistor have the threshold voltage increased when in a standby state, whereby leakage current based upon the subthreshold current is reduced. Furthermore, increase of the depletion layer is reduced since forward bias is established between the source and substrate. Therefore, leakage current will not increase even when short channel effect is significant due to the scale of integration increased in the semiconductor device. Only a small current flows between the source and substrate in active state since a bias of an absolute value lower than the built-in potential is applied therebetween. The threshold voltage is lowered than in a standby state with almost no influence in the operation.
According to another aspect of the present invention, a semiconductor device includes a P channel MOS transistor turned on/off in response to an input signal, an N channel MOS transistor turned on/off in response to an input signal, a first potential supply circuit for supplying a 0 or positive potential to a substrate of a P channel MOS transistor on the basis of a potential of a source electrode thereof when the P channel MOS transistor is turned off, a second potential supply circuit for supplying a negative potential to the substrate of the P channel MOS transistor on the basis of a potential of a source electrode thereof when the P channel MOS transistor is turned on, a third potential supply circuit for supplying a 0 or negative potential to a substrate of the N channel MOS transistor on the basis of a potential of a source electrode thereof when the N channel MOS transistor is turned on, and a fourth potential supply circuit for supplying a positive potential to the substrate of the N channel MOS transistor on the basis of the potential of the source electrode of the N channel MOS transistor thereof when the N channel MOS transistor is turned on.
According to the semiconductor device of the another aspect, the P channel MOS transistor and the N channel MOS transistor have the threshold voltages increased when turned off to reduce leakage current based on the subthreshold current. Furthermore, increase of the depletion layer is reduced since forward bias is established between the source and substrate. Therefore, leakage current will not increase even when short channel effect is significant caused by the scale of integration increased for the semiconductor device. The threshold voltage is lower in an ON state than in an OFF state.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.